au.\*:("IEDA N")
Results 1 to 4 of 4
Selection :
A 64-KBIT DYNAMIC MOS RAMARAI E; IEDA N.1978; I.E.E.E. J. SOLID-STATE CIRCUITS; USA; DA. 1978; VOL. 13; NO 3; PP. 333-338; BIBL. 17 REF.Article
SINGLE TRANSISTOR MOS RAM USING A SHORT-CHANNEL MOS TRANSISTORIEDA N; OHMORI Y; TAKEYIA K et al.1978; I.E.E.E. J. SOLID STATE CIRCUITS; USA; DA. 1978; VOL. 13; NO 2; PP. 218-224; BIBL. 12 REF.Article
A NOVEL MOS PROM USING A HIGHLY RESISTIVE POLY-SI RESISTORTANIMOTO M; MUROTA J; OHMORI Y et al.1980; I.E.E.E. TRANS. ELECTRON DEVICES; USA; DA. 1980; VOL. 27; NO 3; PP. 517-520; BIBL. 7 REF.Article
A REDUNDANCY CIRCUIT FOR A FAULT-TOLERANT 256 K MOS RAMMANO T; WADA M; IEDA N et al.1982; IEEE JOURNAL OF SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1982; VOL. 17; NO 4; PP. 726-731; BIBL. 9 REF.Article